Scientific article

Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker

ContributorsATLAS Semiconductor Tracker Collaboration
Publication date2005

The ABCD3TA is a 128-channel ASIC with binary architecture for the readout of silicon strip particle detectors in the Semiconductor Tracker of the ATLAS experiment at the Large Hadron Collider (LHC). The chip comprises fast front-end and amplitude discriminator circuits using bipolar devices, a binary pipeline for first level trigger latency, a second level derandomising buffer and data compression circuitry based on CMOS devices. It has been designed and fabricated in a BiCMOS radiation resistant process. Extensive testing of the ABCD3TA chips assembled into detector modules show that the design meets the specifications and maintains the required performance after irradiation up to a total ionising dose of 10 Mrad and a 1-MeV neutron equivalent fluence of 2×1014 n/cm2, corresponding to 10 years of operation of the LHC at its design luminosity. Wafer screening and quality assurance procedures have been developed and implemented in large volume production to ensure that the chips assembled into modules meet the rigorous acceptance criteria.

  • Front-end electronics
  • Binary readout
  • Silicon strip detectors
  • Trackingdetectors
  • Radiation damage
  • Application specific integrated circuits
  • Quality assurance
Citation (ISO format)
ATLAS Semiconductor Tracker Collaboration. Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker. In: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2005, vol. 552, n° 3, p. 292–328. doi: 10.1016/j.nima.2005.07.002
Main files (1)
Article (Published version)
ISSN of the journal0168-9002

Technical informations

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