Monolithic active pixel sensors in SiGe BiCMOS combine fast charge collection, low-noise hetero-junction bipolar front-ends and dense CMOS logic on the same substrate, suited for centimeter-scale, sub-nanosecond timing detectors in High-Energy Physics and medical imaging. At this scale, the readout architecture becomes a limiting design step: routing complexity, timing skew and analog-digital coupling constrain the timing and rate performance. This thesis addresses the co-design of asynchronous readout architectures with the front-end, the time digitization and the physical implementation of large-area monolithic pixel Application-Specific Integrated Circuits (ASICs) in SiGe BiCMOS.
The work first develops an analytical framework that brackets two fundamental readout paradigms, packet-based and frame-based, as a function of matrix size, data width and occupancy. Within this framework, projection-based readout with cluster-driven partitioning emerges as a passive spatial-encoding strategy that breaks the quadratic scaling of routing complexity. Two ASICs presented here instantiate the framework with complementary architectural choices.
The full-reticle FASER Preshower ASIC adopts a frame-based readout with hierarchical zero suppression, to cope with occupancies that span from sparse single-pixel background to dense, spatially localized electromagnetic showers. The ASIC combines the per-pixel charge digitization typical of imaging sensors with the sub-nanosecond timing required for shower reconstruction. Local flash converters and distributed readout logic operate in parallel within the active matrix. The characterization of pre-production prototypes exposed several limitations across the chip that the production design addresses systematically, to recover correct operation and match the design specifications. The production chip achieves a dead time of 0.75% at the nominal 500 Hz background rate, meeting the 1% requirement, with a Time-to-Digital Converter quantization step below 200 ps. The Preshower detector operates in the FASER experiment since February 2025.
The 100 µmPET ASIC targets a small-animal imaging scanner based on monolithic pixel sensors with a granularity more than four orders of magnitude better than commercial scintillator-based scanners, combined with sub-nanosecond timing for coincidence selection. Reaching this regime requires the joint optimization of the in-pixel front-end for low threshold, low power and 200 ps time resolution, and of the readout. The 30 × 23 mm² extended-reticle chip implements a fully asynchronous projection-based readout to collect and serialize sparse clusters, without distributing the clock into the sensitive matrix. The digital logic adopts a multi-level buffering pipeline to handle the target event rate of 10 kHz/cm² with a hit-loss probability below 0.0002%. An inter-chip handshake serializes the output of multiple ASICs onto a single line, to limit the material budget. The ASIC characterization exposed design flaws that motivated a post-mask flow, to improve robustness and functionalities of the digital logic without re-fabricating the full mask stack. The modified chip is under submission for the next production run.
The two designs serve as concrete examples of the readout framework introduced in this thesis and show how the same SiGe BiCMOS technology can be used for large-area ASICs with different readouts, tailored to the specific applications.
