A monolithic silicon pixel ASIC prototype, produced in 2024as part of the Horizon 2020 MONOLITH ERC Advanced project, wastested with a 120 GeV/c pion beam. The ASIC features a matrix ofhexagonal pixels with a 100 μm pitch, read by low-noise,high-speed front-end electronics built using 130 nm SiGe BiCMOStechnology. It includes the PicoAD sensor, which employs acontinuous, deep PN junction to generate avalanche gain. Data weretaken across power densities from 0.05 to 2.6 W/cm$^{2}$ and sensorbias voltages from 90 to 180 V. At the highest bias voltage,corresponding to an electron gain of 50, and maximum power density,an efficiency of (99.99 ± 0.01)% was achieved. The timeresolution at this working point was (23.9 ± 0.2) ps beforetime-walk correction, improving to (12.1 ± 0.3) ps aftercorrection.