A second monolithic silicon pixel prototype was produced forthe MONOLITH project. The ASIC contains a matrix of hexagonal pixelswith 100 μm pitch, readout by a low-noise and very fast SiGe HBTfrontend electronics. Wafers with 50 μm thick epilayer of350 Ωcm resistivity were used to produce a fully depletedsensor. Laboratory and testbeam measurements of the analog channelspresent in the pixel matrix show that the sensor has a 130 V widebias-voltage operation plateau at which the efficiency is 99.8%.Although this prototype does not include an internal gain layer, thedesign optimised for timing of the sensor and the front-endelectronics provides a time resolutions of 20 ps.