The nature of dark matter, the imbalance between matter and antimatter, and the properties of the Higgs boson are among the fundamental questions in high-energy physics studied by experiments like ATLAS at the LHC. The high collision rates and massive data volumes produced by the ATLAS experiment require an efficient real-time processing system, the Trigger and Data Acquisition (TDAQ) system. This system is tasked with identifying valuable information within a large background of data and ensuring its storage. To meet these challenges in the High-Luminosity LHC (HL- LHC) era, the ATLAS experiment is undergoing a Phase II upgrade.

This thesis focuses on developing FPGA-based low-latency and high-throughput solutions for various components of the Phase II TDAQ upgrade. The projects presented include the firmware development for the Central Trigger Processor (CTP) readout and data buffering feasibility studies; firmware development for the Pattern Recognition Mezzanine (PRM) and hardware validation of the system; exploration of FPGA accelerator capabilities in a data center architecture; and the development and validation of the Vitis accelerator backend for HLS4ML to automate the generation of HLS4ML projects targeting CPU-FPGA accelerator setups, including its application with an ML-based algorithm.

The work contributes to the ATLAS experiment’s goal of exploring fundamental physics phenomena, including the Standard Model and potential new physics. These developments enhance the efficiency and capability of the TDAQ system, preparing it to handle the increasing data rates and complexities of future upgrades.