A 128 channel ASIC is being designed for the read-out of silicon strip detectors in the LHC ATLAS Experiment at CERN. The chip is based on work already done for the analogue readout of detectors using pre-amps, shapers and capacitor arrays to form an analogue delay buffer. In addition this chip will have a 128 channel Wilkinson ADC based on the SVX Detector design to digitise all channels in parallel and sparsify the data according to a digitally set threshold. The chip will be fabricated in the AMS 1.2 micron technology by the end of 1995 to prove the architecture before being converted to a Radiation Hardened process.